Field
The present invention relates to a tunneling field-effect transistor and a fabrication method thereof, and more particularly to a tunneling field-effect transistor having a plurality of vertically stacked nanowires and a fabrication method thereof.
Description of the Related Art
A semiconductor technology based on a channel formed by a gate voltage and a metal oxide semiconductor field effect transistor (hereinafter, referred to as MOSFET) which is driven in the form of carriers drifting by a drain voltage has developed innovatively.
Recently, researches are actively being devoted to a tunneling field-effect transistor (hereinafter, referred to as TFET) using tunneling between bands. The TFET is driven by a tunneling of carriers, based on energy band characteristics caused by the gate voltage and the drain voltage. Compared with the MOSFET, the TFET has a superb sub-threshold slope (SS) characteristic. This is an indicator to evaluate the performance of the transistor as a switch. The less the value of the SS is, the less standby power the TFET consumes. While an existing MOSFET has 60 mV/dec, the TFET has a value less than 60 mV/dec.
However, unlike the MOSFET using a drift mechanism (FIGS. 14A and 14B), the TFET using a tunneling mechanism (FIGS. 15A and 15B) has a limitation of having a low driving current. The driving current is related to the operating speed of the transistor. A higher driving current allows the transistor to perform a faster switch function.
One method for solving the low driving current of the TFET is to shorten the length of the gate. However, the shortened length of the gate of the TFET brings about a new problem of a short channel effect.
Another method for solving the low driving current of the TFET is to increase a channel area of the TFET. This intends to increase the driving current by increasing the channel area. However, this method goes against a current trend in which the transistor becomes smaller and has a higher degree of integration of a semiconductor chip.